Elevate your career as a UVM Verification Engineer with Synopsys, focusing on innovative memory interface IP development. Enjoy a collaborative environment aimed at tackling complex challenges in silicon design.
At Synopsys, you will thrive as part of the IP Group, utilizing your expertise in SystemVerilog and UVM. This role emphasizes developing robust verification testplans and testbench infrastructures, collaborating with architecture teams, and mentoring junior engineers. You will help ensure quality and performance of next-generation technologies.
Key Responsibilities:
• Develop comprehensive verification testplans for memory interface IP
• Design and implement UVM testbench infrastructure
• Collaborate through technical reviews with engineering teams
• Diagnose complex verification challenges using advanced tools
• Mentor junior engineers in best practices and technical skills
Requirements:
• Proficient in SystemVerilog and UVM
• Bachelor’s degree in...