Join Synopsys as a Senior Engineer in Analog Layout, pushing the boundaries of semiconductor technology through innovation and collaboration across global teams.
This role encompasses developing advanced methodologies in analog layout design, with a focus on cutting-edge nodes like sub-5nm FinFet. You will leverage your scripting capabilities in Tcl, Perl, and Python to enhance design efficiency and support IP integration. Engage in training and fostering collaborative practices to streamline workflows.
Key Responsibilities:
• Propose advanced layout design techniques and solutions
• Verify existing designs for PDK impacts
• Collaborate with global organizations for design optimization
• Utilize and enhance in-house design tools
• Support training for new layout methodologies
Requirements:
• BS/MS in Electrical Engineering or related field
• 5+ years of custom analog design experience
• Expertise in Tcl, Perl, and Python scripting
• Experience debugg...