+ Physical layout design for chiptop, subsystem or partition level, including Synthesis, Place & Route, Physical verification, Static Timing Check, Power design network, Power Verification, ... + Collaborate with related teams to finish design within define schedule. + Manage team, working with team to achieve Tape Out target. + Sharing technical expertise and build-up team capability.
Qualifications
+ At least 6 years experience in semiconductor design, Physical Layout design. + Solid knowledge in using EDA tool (Synopsys, Cadence, Mentor, ...). + Good written and oral communication (in English) & interpersonal skills. + Strong team-oriented working and good relationship-building with others. + Good communication skills as well as problem solving skills. + Experience in scripting languages such as C-Shell, Perl, Tcl or phython is plus. + Have experience in logic related design...