Advance your career as a Senior ASIC Physical Design Engineer at a leading tech firm. Bring 8+ years of backend expertise to optimize physical design workflows and collaborate effectively.
In this senior-level role, you will leverage your extensive experience from netlist to GDSII while focusing on Place & Route, timing closure, and precise tool optimization. Collaboration with cross-functional teams is essential, utilizing hands-on skills in cutting-edge designs like 7nm and 5nm to achieve project goals.
Key Responsibilities:
• Optimize Place & Route for efficient design flow
• Ensure timing closure with setup/hold and ECO
• Perform Static Timing Analysis and generate reports
• Conduct power integrity analysis and implement optimizations
• Collaborate effectively with RTL and DFT teams
Requirements:
• 8+ years in ASIC Physical Design or similar field
• Proficiency in Tcl, Python, or related scripting languages
• Strong experience in clock tree synthesi...