Elevate your career at Alphawave Semi as an RTL Design Engineer, specializing in complex IP design and timing optimization strategies. Contribute to advancements in AI and 5G data communication technologies.
In this critical role, you will manage the front-to-back implementation workflow for high-performance computing systems. Your expertise in SystemVerilog will be essential as you handle timing constraints, conduct synthesis, and collaborate closely with cross-functional teams for innovative solutions. The role promises to be both challenging and rewarding as you enhance the quality of design and technology.
Key Responsibilities:
• Own the implementation of complex IP from RTL to P&R
• Conduct synthesis and analyze QoR timing reports
• Manage timing constraints and address violations
• Define clock architecture and CTS targets
• Integrate AI tools for log analysis
Requirements:
• Bachelor's/Master's in Computer or Electrical Engineering
• Proficiency in ...