BairesDev is seeking an experienced RTL Design Engineer in Bogotá, Colombia. In this role, you will design register-transfer-level logic for ASIC chips, contributing to the digital architecture and ensuring high performance and reliability. Ideal candidates will have over 4 years of experience in RTL or ASIC design and a strong proficiency in Verilog and SystemVerilog. The position offers a fully remote work environment with excellent compensation and flexible hours.
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