Join to apply for the Design Verification role at W3Global

1 day ago Be among the first 25 applicants

Must: System Verilog & UVM

Base pay range

CA$60.00/hr - CA$70.00/hr

Description

• DV engineer with 3+-13 yrs of experience.
• Verification of display IP used in graphics card.
• IP/SS and end‑to‑end testing for these blocks.
• Experience in DV flow including SV and UVM.

Seniority level

• Mid-Senior level

Employment type

• Contract

Job function

• Information Technology
• Staffing and Recruiting

Referrals increase your chances of interviewing at W3Global by 2x.

Get notified about new Verification Specialist jobs in Markham, Ontario, Canada .