Job TitleJR****** – DRAM Design Tech Layout EngineerPosition Level: Layout/Mask Designer E3 – Relocation Level: TBDResponsibilitiesDesign and develop IP layouts used in DRAM chips.Perform layout verification (LVS/DRC/EM), quality check and documentation.Deliver block‐level layouts on time with acceptable quality.Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and breakthroughs in a multi‐project environment.Guide and lead team members in the execution of sub‐block layouts and review their work.Contribute to effective project management.Plan and detail layouts, presenting material for global teams to review.Collaborate with engineering teams in India, Japan, the US, and other global teams to ensure layout project success.Minimum QualificationsBE/BTech or MTech in Electronic/VLSI Engineering or equivalent; exceptionally talented Diploma holders in electronic or VLSI engineering may also be considered.3+ years of...