Position Overview We are seeking an experienced DFT Engineer with strong expertise in Design-for-Test methodologies for complex ASIC/SoC designs. The ideal candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage, manufacturability, and silicon quality for next-generation semiconductor products. The role requires deep understanding of scan insertion, ATPG, MBIST, JTAG, compression techniques, and SoC-level DFT integration flows. Key Responsibilities Define and implement DFT architecture for complex ASIC/SoC designs. Perform scan insertion, scan stitching, and DFT integration activities. Develop and validate DFT features including: Scan ATPG MBIST LBIST JTAG/Boundary Scan Test Compression Work on DFT verification and debug activities. Generate and analyse ATPG patterns and coverage reports. Collaborate closely with RTL Design, Physical Design, STA, and Validation teams. Support gate-level simulations and silicon bring-up activities. Dr...