Elevate your expertise as a Senior Layout Design Engineer specializing in analog and mixed-signal CMOS circuit layouts at Synopsys. Drive high-speed SerDes interface development in a collaborative atmosphere.
This senior-level role requires a minimum of 5 years of experience in analog CMOS layout design. You will focus on optimizing high-performance layouts to ensure compliance with foundry standards and mitigate signal integrity issues. Your collaboration with global engineering teams will enhance device performance and reliability, utilizing innovative layout methodologies.
Key Responsibilities: • Implement analog and mixed-signal CMOS layouts for SerDes • Collaborate closely with circuit designers for effective layout development • Execute thorough floor planning and layout verification processes • Address signal integrity and ESD challenges effectively • Maintain updated documentation for layout best practices